The present specification relates to a memory device, an integrated circuit as well as to an electronic device. The specification further refers to a method of forming an integrated circuit.
A shrink of minimum feature sizes of integrated circuits allows to decrease the costs per integrated circuit by a corresponding increase of the package density per wafer. The miniaturization of integrated circuits may also affect conductive lines.
By way of example, also the width of a source line between selected transistors may be decreased when scaling a NAND memory cell array to smaller minimum feature sizes.
Scaling of conductive lines introduces challenges in view of, for example, conductivity requirements or critical dimensions that have to be handled in order to meet designated reliability demands.
Generally, an integrated circuit, which has a high reliability in its operation characteristic is desired.